AMD’s Zen 2 architecture has been an incredible success for the company and is taking the desktop world by storm thanks to the ryzen 3000 series CPUs, and the server market is also facing serious disruption thanks to AMD increasing the core count to 64 cores with its Milan range of processors, while also improving performance across the board.
In the past, AMD confirmed that Zen 3, Zen 4 and even Zen 5 are in the works, with the next-generation server chips from the company (the successor to Milan), known as Genoa. But, when AMD first launched both the original Ryzen CPUs and the first-gen of Epyc, Lisa Su promised that there would be forwards/backwards compatibility until 2020.
So, we’ve known that if you have bought say an X370 motherboard back in 2017 along with a Ryzen 7 1700X, you should be able to switch that CPU out with say Ryzen 7 4700X in 2020, as long as you do a BIOS update. We also knew thanks to comments from Forrest Norrod in a couple of different interviews that Milan would continue to support DDr4, because of their promise that they would retain socket-compatibility with existing boards for that generation.
We also knew that Zen 3 would leverage TSMC’s 7nm+ process, which is similar-ish to the current 7nm process, albeit uses EUV for some of its layers, and thus improve density, power consumption and performance around 10 – 15 percent (based on TSMC’s own estimates).
Thanks to a presentation at the HPC-AI Advisory Council in the UK though, we now know a lot more details of about not just Zen 3, but also Milan and even its successors. It’s quite surprising AMD opted to release these details so early – but for those interested in technology, we’re not complaining.
Let’s start things with the stuff we already know, but is reconfirmed – DDR4 support (though supported memory speeds weren’t mentioned), SP3 socket (the same as the older generations), 7nm+ (there was a typo in this roadmap, but it was confirmed in the video presentation that it is 7nm+), PCIe 3 and 4 support (though the number of lanes wasn’t specified).
For new information though – it retains the same TDP as the second generation – between 120 and 225W. We also see the same number of cores too, 64 Cores / 2x. For just a long second I wondered if that was a reference to the number of sockets supported, or if this was confirmation of the SMT support – and right there in the notes on the bottom left, it was confirmed – it was SMT.
So this is a confirmation that the SMT-2 remains, and for Milan at least, SMT-4 isn’t featured. Zen 3 featuring SMT-4 has been long-rumoured, and digging into my own sources in general told me they either didn’t think it was featured, or was only for specific chips (so the most expensive Epyc CPUs), this seems to have confirmed that it isn’t there in any of the upcoming Zen 3 SKUs.
This also confirms (in theory, we’ll get to that), we’ll only see 9 dies on the CPU – pretty much similar to how say… Epyc Rome looks. It was Charlie over at SemiAccurate who’d originally said that there are more dies on Milan (he believed up to 15), but this is probably not true… unless they’re something not CPU related, such as GPU cores or HBM2 (this isn’t a piece of info I heard, to be clear… I’m just providing a way to balance his usually good info with this official confirmation).
Another huge thing we can see is a shot of the CCX and CPU layout compared to that of Rome, and the differences in the Level 3 cache between a Zen 2 CCX and Zen 3 CCX are palpable. The second-generation Zen did numerous things to the architecture which we’ve discussed a lot in the past, but one big change was the Level 3 cache, which was doubled in size.
But, essentially each ‘chiplet’ was comprised of 8 CPU cores, and those 8 cores were then further split into two ‘CCXs’, each housing its own 4 cores and 16MB level 3 cache (so 4 cores and 16MB x 2 CCXs = 8 cores and 32MB total). Here though, it seems the plan is different, and that the Level 3 cache is going to be “at least” 32MB, but the CCX looks unified.
So essentially the CCX becomes 8 CPU cores, and they all have access (I assume with equal latency) to the Level 3 cache pool, along with their own L2 and L1 caches of course. In theory, the impact on latency should be pretty profound and should help CPUs with lower core counts too. For example, an 8 core Ryzen 4000 CPU would benefit heavily.
This also has lots of potential for APUs too and makes me wonder if AMD will change the core count in APUs (giving them a bump).
One other possible piece of speculation is that Charlie over at SemiAccurate released an article earlier this year claiming AMD’s strategy for designing CPU cores is evolving, and we will say a diverging design between the Zen cores found in say, Ryzen versus Epyc. Further, there will be customization based on usage scenario too.
This is somewhat backed up by a few slides released by AMD on the subject of Frontier, a supercomputer they’re working on with Cray and the US Department of Energy. In this documentation it specifically mentions a custom design – so (and this is pure speculation), some customers get SMT-4 and higher die count chips… though once again, this is pure speculation and an attempt to make the old rumors fit.
Let’s also bring Genoa / Zen 4 into the equation, although we know much less about this than we do Zen 3 and Milan. AMD confirmed that we’ll see a different socket (SP5), and currently they’re still adding features to the chips (meaning it’s not finalized). Zen 4 also features support for next-gen memory, and being blunt, DDR5 is really the obvious next-gen memory.
Although (and this is NOT official info, just a bit of speculation), it’s possible we could see some variants with a few HBM dies on there, especially if AMD add GPU cores to the mix, though – this is pure “what if” speculation on my part. Zen 4 and Genoa will not support older boards, and that will, of course, extend to the desktop too.
If I had to speculate – with DDR5 memory, we could see more CPU cores. Just like you can’t build say an RX 5700 XT with 128-bit 7gbps memory without the constrained performance of the GPU cores because of lack of bandwidth, you can’t just keep putting more CPU cores onto a die without expanding the amount of bandwidth too.
It’ll be very interesting to see what type of performance jump we can expect with Zen and Zen 4 based products, given Intel will be racing to catch up with their future CPU cores such as Sunny Cove. We’ve seen AMD claim that Sunny Cove and Zen 3 will be close to one another in terms of performance per watt, but until we have the launch of the product – we can only take AMD’s word for it.