In case you missed the news, AMD’s next foray into the HPC and server market will be Epyc 2, known as Rome. It is an up to 64 core (128 thread) monster, built on the companies 7nm Zen 2 architecture which will debut next year. Unlike the Zen+ architecture found in both the companies Ryzen 2000 and ThreadRipper 2 series, Zen 2 has numerous fundamental changes under the hood which drastically boost IPC, clock speed and overall means that these processors are eagerly anticipated for both desktop and the server space.
We covered a lot of the information AMD released at their Next Horizon event regarding 7nm, Rome and Zen 2 here, so if you want a quick catch up feel free to check it out!
So then, let’s discuss today’s leak which can be found on SiSoft Sandra’s Database, courtesy of a SuperMicro Super Server (H12DST-PS). We see Sisoft Sandra detect the AMD Rome CPU as “2x AMD Eng Sample: 2S1404E2VJUG5_20/14_N”. There are a few important things immediately clear in the code name – the first is that well… it’s an engineering sample, so take some (or all) of this stuff is subject to change, particularly clock speed.
But we can see the socket and processor configuration info here, including the 20 / 14, and that is almost certainly (judging from previous chips, along with the actual reported base speed in the benchmark software) the Turbo and Base clocks, respectively.
In the result ID, after the name we see “(64C 1.4GHz, 800MHz IMC, 64x 512kB L2, 16x 16MB L3)”. So that, of course, confirms that the chip is running at 64C, with the IMC at 800MHZ. Each of the Zen 2 cores contains the same amount of Level 2 cache as previous Zen processors, 512KB.
But, the biggest thing here is we notice the 16x 16MB. So this means one of three things; the first is that it is not being read right by Sisoft Sandra (which is entirely possible and could indeed be kinda likely). The second is that the CCX configuration of Zen 2 is the same as Zen and Zen+, so that there aren’t 8 chips in each CCX, but instead just 4. Another possibility is that the modules themselves do have 8 cores total but are made up of two smaller CCX building blocks, and that’s why the level 3 cache is being read that way (so basically, each 4 cores has its ‘own’ Level 3 cache, but that could still be shared with the other 4 cores inside that particularly cluster).
Below is a representation of the Zen basic CCX design, this is for the original Summit Ridge (such as the Ryzen 1700) but the principal remains the same. Two CCXs come together to form a larger whole.
Here is a shot AMD released for the upcoming Zen 2, and how its ‘chiplets’ are designed. Each CPU core is on 7nm, with a 14nm IO controller. The number of cores and how these connect is still somewhat of a mystery.
We’ll be putting out a deeper dive on Zen 2 soon, but for now, it’s fair to say that no matter what AMD has done, it’ll be exciting. As we concluded in another video and article where we put an Intel I9-9900K up against a Ryzen 7 2700X with the two processors running at the same clock frequency, a 10 – 15 percent IPC boost (along with a modest clock speed jump) will put Intel on shaky ground, not just in the server space, but also mainstream.
How things play out if AMD has the advantage for several months in terms of pricing will be of extreme interest. There are certainly a number of other questions; not least of all will we see a core count increase on the AM4 platform, and will that mean that Ryzen 3000 will not be compatible with older motherboards. We also went over a recent Ryzen 3700U leak a few days ago, but that does appear to closely match the current Ryzen 7 2700U.
AMD has typically done rather well in the value market, with the 2700X currently retailing at about half the price of the I9-9900K. We also concluded that with a card such as the RTX 2070, there is no real gaming performance difference between the two processors.