It seems like the excitement for Zen 2 hasn’t even stopped and the hype for Zen 3 is already starting. AMD has been a merciless execution machine, and timing and staggering their product launches perfectly to not just keep the hype up, but also ensure that each launch goes off as smoothly as possible. The company has already confirmed that Zen 3 won’t be a subtle upgrade, quashing rumors that Zen 3 would be more like Zen+, a small tweak here or there, but nothing astounding.
One of my earlier leaks from a reliable source claims that the IPC gains for Zen 3 ‘are at least 8 percent’, but recently AMD’s own Forrest Norrod confirmed this, revealing that the performance for Zen 3 would be right in-line with what you’d expect for an entirely new CPU architecture and the company were not going to give Intel any time to start mounting a defense.
We also saw AMD accidentally plop a video online (swiftly removing it) called “innovator insights”, designed to inform the HPC crowd of AMD’s plans in the high-end space. AMD didn’t fully elaborate on Zen 3’s architecture of course, but they did confirm that there’d be some rather radical tweaks to the Level 3 cache of the CPU and that the CCX layout of the chip would change. This new layout hinted one thing – AMD was keen to reduce latency as much as possible.
More recently, another source told me that the IPC gains for Zen 3 were higher than what my first source claimed (the first source said at least 8 percent, but the second claimed 10 percent at least), while a third source said that he wouldn’t be surprised if the performance hit closer to 15 – 17 percent depending upon the workload, but wouldn’t further elaborate. I reported this first in the same video I detailed a leak from BitsNChips English Twitter account, where he provided insight that the Zen 3 Level 1 cache would see up to a 40 percent increase in bandwidth.
I wrote to him and started speaking to him about the IPC gains of my sources, and he said it sounded right (about ten percent is what he’d heard too), but he said scientific workloads were much greater but didn’t provide more info as to why. I started digging around, writing to several sources. One got back to me pretty quickly – this source was pretty accurate in the past about Zen 2, but he was a bit more candid this time, and just agreed but didn’t provide any greater detail.
I then heard back from another source, who told me that he believes that’s accurate and down to enhancements on the Floating Point units of Zen 3, although he wasn’t specifically aware as to what the changes are. I will leave speculation alone in this particular post as to what the enhancements will be, but this seems to build on what AMD was doing with Zen 2. You might recall the company put a lot of emphasis on the FP increase for Zen 2, and AMD seems intent to pursue this heavily as the Zen architecture continues to mature.
In the image above, AMD details the changes for the Floating Point Unit for the Zen 2 architecture, and as you can see bullet point number one was doubling the width of the FPU from the older generation Zen CPUs. This made AMD’s server offerings (Rome) extremely tempting to data centers and HPC.
Although we still are far from a complete picture, it looks like Zen 3 will have the same number of both threads and processor cores (so SMT-2 support and let’s say 16 cores for Ryzen 4000), but Zen 3 will focus even more on reducing latency across the CCX and really pushing the performance to the limit with floating-point. We can presume that with these enhancements, the chip will be a monster at mixed FP and Int workloads. I have also heard that the Engineering Silicon is a few hundred MHz faster than Zen 2, so nothing startling, and will likely mean we still miss out on 5GHz, but with these types of tweaks… it might not matter other than 5GHz being a very nice PR number.
In the here and now though, AMD’s product portfolio is really compelling. We recently investigated an all AMD build comprised of a Ryzen 7 3700X and an RX 5700 and the performance is just crazy given the pricing, and would have been unheard of just a few years ago without spending several times the amount of money.
Ryzen 4000 (which uses Zen 3) will also be the final CPUs on the AM4 platform, so if these rumors and reports are accurate, AMD will be sending the platform out with a bang. Ryzen 5000 (assuming it is called Ryzen 5000) and onwards will use an entirely different socket and platform, and we can presume it will support new standards such as DDR5.
The biggest problem right now is AMD is really lacking a high-end GPU, with Navi 12 (once thought to be Big Navi) now reported to be nothing more than Navi 10, albeit with support for HBM2 and designed for Apple. The good news though is that Navi 23 and Navi 21 are confirmed to exist, and according to my sources are being called ‘Nvidia Killers’.
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